Generation of High-Speed Network Device from High-Level Description

Author: Ing. Pavel Benáček, Ph.D.
Email: benacpav@fit.cvut.cz

Abstract

OpenFlow, as the most popular embodiment of Software-Defined Networking, provides a way to network dataplane configuration at runtime. The OpenFlow specification strictly defines a set of supported protocols and actions for further processing of incoming traffic (i.e., switches are still mostly fixed). However, modern requirements on networking hard- ware have a dynamic character and administrators of high-end networks want to react to new protocols, security threats, novel approaches in traffic engineering, and so on. This isn’t feasible with static network hardware and leads to the need to replace the hardware more often than desired.

The aim of my dissertation thesis is to provide the process of mapping from abstract language to the architecture of network device which is suitable for automatic generation and capable to hit processing speed of 100Gbps in single FPGA. The architecture of network device is based on predefined interfaces and modules which are connected to a high-speed processing pipeline. The text provides details of transformation process to individual blocks of network device: parser, deparser, Match+Action table, Match+Action router and Match+Action group. The text also demonstrates the usage of High-Level Synthesis tools to provide a custom processing engine which is capable to hit speed of 100 Gbps. Finally, the text provides three use cases for demonstration of flexibility and easy extensibility with new protocols and actions. Each use case was described in P4 language, translated to VHDL and tested in real hardware environment. The results show that generated devices are capable to meet throughput in range from 77.6 to 100 Gbps.

Keywords

FPGA, High-Level Synthesis, Transformation, P4, SDN, High-Speed Computer Net- works, 100 Gbps, VHSIC Hardware Description Language.

Links

Acknowledgements

First of all, I would like to express my thanks to my dissertation thesis supervisors, Ing. Viktor Puš, Ph.D. and doc. Ing. Hana Kubátová, CSc., for their support, valuable comments and guidance. They have been a constant source of encouragement and insight during my research and helped me with numerous problems and professional advancements.

Special thanks go to the staff of the Liberouter project, funded by CESNET, and the Department of Digital Design of the Czech Technical University in Prague, who maintained a pleasant and flexible working environment for my research. I would like to express special thanks to the management of both institutions for providing of the funding for my research. My research has been partially supported by the Czech Technical University in Prague, grants No. SGS14/102/OHK3/042/14, No. SGS14/105/OHK3/1T/18, No. SGS15/122/OHK3/1T/18, by the Ministry of Education, Youth, and Sports of the Czech Republic under research programs CESNET Large Infrastructure project No. LM2010005, CESNET E-infrastructure project No. LM2015042, by the European Union in the context of the BEBA project (Grant Agreement: 644122) and by the projects TA03010561, TH01010229 funded by the Technology Agency of the Czech Republic.

I would like to express thanks to my colleagues from the Liberouter group, namely Ing. Lukáš Kekely, Ing.Jan Kořenek,Ph.D., Ing.Martin Žádník,Ph.D., Ing. Tomáš Čejka and others, for their valuable comments and motivation in my research.

My greatest thanks go to Petra and my family members for their infinite patience, care, love and support. Finally, I would like to greatly thank to my father MVDr. Zdeněk Benáček for his love, patience and amazing childhood because he suddenly died after the long disease on 3 December 2015 .